//__________________________________________________________________
//
//  Module      :   ASYN_FIFO
//              
//  By          :   Kejie
//  E-mail      :   Kejie1208@126.com
//  Created     :   08/12/10 
//  Read Mode   :   First-Word Fall-Through
//                  All Outputs are Registed
//  First-Word
//  Fall-Through
//  Notes:          The First Word into the fifo will be valid in the w_data,
//                  while the r_empty is fall down.
//                  And if r_re is assigned some time, 
//                  then in the next Cycle 
//                  the w_data will be the Second Word  
//___________________________________________________________________

`timescale 1ns/1ns

module  syn_fwft_fifo_d256_w289 #(
    
parameter   L=8,        //Fifo Depth = 2^L+2;
parameter   DW=289       //Data Width = DW;
)
(
  
  input                   clk,
  input                   clr,
  input     [9:0]       ram_2p_cfg_register,
                          
  input       [DW-1:0]    w_data,
  input                   w_we,
  output reg              w_full,
  output reg              w_afull,
                          
  output reg  [DW-1:0]    r_data,
  input                   r_re,
  output reg              r_empty,
  output reg              r_aempty
);

wire            rst_n         ;
wire [L-1:0]    ram_rd_addr   ;
wire [L-1:0]    ram_wr_addr   ;
wire [L-1:0]    ram_rd_addr_DL;
wire            ram_we_n      ;
wire a;
assign rst_n = clr;

    DW_fifoctl_s1_sf #(
      .depth(256), 
      .ae_level(1), 
      .af_level(48), 
      .err_mode(0), 
      .rst_mode(0)) 
    FIFO_CTL(
      .clk(clk),
      .rst_n(rst_n),
      .push_req_n(~w_we),
      .pop_req_n(~r_re),
      .diag_n(1'b1),
      .empty(r_empty),
      .almost_empty(r_aempty),
      .half_full(),
      .almost_full(w_afull),
      .full(w_full),
      .error(),
      .we_n(ram_we_n),
      .wr_addr(ram_wr_addr),
      .rd_addr(ram_rd_addr)
      );

assign ram_rd_addr_DL = (r_re) ? ram_rd_addr + 1'd1 : ram_rd_addr;

ram_2p_d256_w290_wrapper U_ram_2p_d256_w290_wrapper (
	.clk(clk),
    .ram_2p_cfg_register(ram_2p_cfg_register),
	.wren(~ram_we_n),
	.waddr(ram_wr_addr),
	.wdata({1'b0,w_data}),
	.rden(1'b1),
	.raddr(ram_rd_addr_DL),
	.rdata({a,r_data})
	);

endmodule  

